// $Id: hardware.h,v 1.12.4.3 2003/08/19 16:51:58 philipb Exp $ /* tab:4 * "Copyright (c) 2000-2003 The Regents of the University of California. * All rights reserved. * * Permission to use, copy, modify, and distribute this software and its * documentation for any purpose, without fee, and without written agreement is * hereby granted, provided that the above copyright notice, the following * two paragraphs and the author appear in all copies of this software. * * IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO ANY PARTY FOR * DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING OUT * OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF THE UNIVERSITY OF * CALIFORNIA HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * THE UNIVERSITY OF CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES, * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY * AND FITNESS FOR A PARTICULAR PURPOSE. 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If you do not agree to this license, do not download, * install, copy or use the software. * * Intel Open Source License * * Copyright (c) 2002 Intel Corporation * All rights reserved. * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are * met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * Neither the name of the Intel Corporation nor the names of its * contributors may be used to endorse or promote products derived from * this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE INTEL OR ITS * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * */ /* * * $Id: hardware.h,v 1.12.4.3 2003/08/19 16:51:58 philipb Exp $ * */ #ifndef TOSH_HARDWARE_H #define TOSH_HARDWARE_H #ifndef TOSH_HARDWARE_MICA2 #define TOSH_HARDWARE_MICA2 #endif // tosh hardware #define TOSH_NEW_AVRLIBC // mica128 requires avrlibc v. 20021209 or greater #include #include "CC1000Const.h" // avrlibc may define ADC as a 16-bit register read. This collides with the nesc // ADC interface name uint16_t inline getADC() { return inw(ADC); } #undef ADC #define TOSH_CYCLE_TIME_NS 136 // each nop is 1 clock cycle // 1 clock cycle on mica2 == 136ns void inline TOSH_wait_250ns() { asm volatile ("nop" ::); asm volatile ("nop" ::); } void inline TOSH_uwait(int u_sec) { while (u_sec > 0) { asm volatile ("nop" ::); asm volatile ("nop" ::); asm volatile ("nop" ::); asm volatile ("nop" ::); asm volatile ("nop" ::); asm volatile ("nop" ::); asm volatile ("nop" ::); asm volatile ("nop" ::); u_sec--; } } // LED assignments TOSH_ASSIGN_PIN(RED_LED, A, 2); TOSH_ASSIGN_PIN(GREEN_LED, A, 1); TOSH_ASSIGN_PIN(YELLOW_LED, A, 0); TOSH_ASSIGN_PIN(SERIAL_ID, A, 4); TOSH_ASSIGN_PIN(BAT_MON, A, 5); TOSH_ASSIGN_PIN(THERM_PWR, A, 7); // ChipCon control assignments TOSH_ASSIGN_PIN(CC_CHP_OUT, A, 6); // chipcon CHP_OUT TOSH_ASSIGN_PIN(CC_PDATA, D, 7); // chipcon PDATA TOSH_ASSIGN_PIN(CC_PCLK, D, 6); // chipcon PCLK TOSH_ASSIGN_PIN(CC_PALE, D, 4); // chipcon PALE // Flash assignments TOSH_ASSIGN_PIN(FLASH_SELECT, A, 3); TOSH_ASSIGN_PIN(FLASH_CLK, D, 5); TOSH_ASSIGN_PIN(FLASH_OUT, D, 3); TOSH_ASSIGN_PIN(FLASH_IN, D, 2); // interrupt assignments TOSH_ASSIGN_PIN(INT0, E, 4); TOSH_ASSIGN_PIN(INT1, E, 5); TOSH_ASSIGN_PIN(INT2, E, 6); TOSH_ASSIGN_PIN(INT3, E, 7); // spibus assignments TOSH_ASSIGN_PIN(MOSI, B, 2); TOSH_ASSIGN_PIN(MISO, B, 3); TOSH_ASSIGN_PIN(SPI_OC1C, B, 7); TOSH_ASSIGN_PIN(SPI_SCK, B, 1); // power control assignments TOSH_ASSIGN_PIN(PW0, C, 0); TOSH_ASSIGN_PIN(PW1, C, 1); TOSH_ASSIGN_PIN(PW2, C, 2); TOSH_ASSIGN_PIN(PW3, C, 3); TOSH_ASSIGN_PIN(PW4, C, 4); TOSH_ASSIGN_PIN(PW5, C, 5); TOSH_ASSIGN_PIN(PW6, C, 6); TOSH_ASSIGN_PIN(PW7, C, 7); // i2c bus assignments TOSH_ASSIGN_PIN(I2C_BUS1_SCL, D, 0); TOSH_ASSIGN_PIN(I2C_BUS1_SDA, D, 1); // uart assignments TOSH_ASSIGN_PIN(UART_RXD0, E, 0); TOSH_ASSIGN_PIN(UART_TXD0, E, 1); TOSH_ASSIGN_PIN(UART_XCK0, E, 2) TOSH_ASSIGN_PIN(UART_RXD1, D, 2); TOSH_ASSIGN_PIN(UART_TXD1, D, 3); TOSH_ASSIGN_PIN(UART_XCK1, D, 5); void TOSH_SET_PIN_DIRECTIONS(void) { /* outp(0x00, DDRA); outp(0x00, DDRB); outp(0x00, DDRD); outp(0x02, DDRE); outp(0x02, PORTE); */ TOSH_MAKE_RED_LED_OUTPUT(); TOSH_MAKE_YELLOW_LED_OUTPUT(); TOSH_MAKE_GREEN_LED_OUTPUT(); TOSH_MAKE_CC_CHP_OUT_INPUT(); // modified for mica2 series TOSH_MAKE_PW7_OUTPUT(); TOSH_MAKE_PW6_OUTPUT(); TOSH_MAKE_PW5_OUTPUT(); TOSH_MAKE_PW4_OUTPUT(); TOSH_MAKE_PW3_OUTPUT(); TOSH_MAKE_PW2_OUTPUT(); TOSH_MAKE_PW1_OUTPUT(); TOSH_MAKE_PW0_OUTPUT(); TOSH_MAKE_CC_PALE_OUTPUT(); TOSH_MAKE_CC_PDATA_OUTPUT(); TOSH_MAKE_CC_PCLK_OUTPUT(); TOSH_MAKE_MISO_INPUT(); TOSH_MAKE_SPI_OC1C_INPUT(); TOSH_MAKE_SERIAL_ID_INPUT(); TOSH_CLR_SERIAL_ID_PIN(); // Prevent sourcing current TOSH_MAKE_FLASH_SELECT_OUTPUT(); TOSH_MAKE_FLASH_OUT_OUTPUT(); TOSH_MAKE_FLASH_CLK_OUTPUT(); TOSH_SET_FLASH_SELECT_PIN(); TOSH_SET_RED_LED_PIN(); TOSH_SET_YELLOW_LED_PIN(); TOSH_SET_GREEN_LED_PIN(); } enum { TOSH_ADC_PORTMAPSIZE = 12 }; enum { TOSH_ACTUAL_CC_RSSI_PORT = 0, TOSH_ACTUAL_VOLTAGE_PORT = 7, TOSH_ACTUAL_BANDGAP_PORT = 30, // 1.23 Fixed bandgap reference TOSH_ACTUAL_GND_PORT = 31 // GND }; enum { TOS_ADC_CC_RSSI_PORT = 0, TOS_ADC_VOLTAGE_PORT = 7, TOS_ADC_BANDGAP_PORT = 10, TOS_ADC_GND_PORT = 11 }; #endif //TOSH_HARDWARE_H